Data processor memory systems can service requests from its central processing unit (CPU) or from external masters. Requests from external masters will arrive on a slave DMA port and termed as slave DMAs.
At any given time there could be multiple requests in flight inside memory system from various masters. These requests needs to be serviced based on requestor permissions and access permissions of the accessed memory location. If an access attempt violates access permission, the corresponding requestor needs to be notified and an exception taken. Exceptions also need to be taken on various types of error detection and correction (EDC) errors in data. These exceptions typically will be routed to interrupt controller to enable corrective action based on the type of exception.
These criticality of these exceptions varies based on the requestor of the access attempt that caused the exception. Existing solutions do not have priority based exception handling mechanism based on the identity of the requestor. This could result in the exception controller taking non-trivial corrective actions when the exception is from a lower-priority requestor like external master. Other solutions implement priority among different requests from a single master.